cpldfit:  version I.34                              Xilinx Inc.
                                  Fitter Report
Design Name: Top_module                          Date:  5- 6-2008,  2:03PM
Device Used: XCR3064XL-6-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
40 /64  ( 62%) 118 /192  ( 61%) 84  /160  ( 52%) 28 /64  ( 44%) 16 /32  ( 50%)

** Function Block Resources **

Function  Mcells    FB Inps   Pterms    IO        GCK       
Block     Used/Tot  Used/Tot  Used/Tot  Used/Tot  Used/Tot  
FB1        16/16*    25/40     42/48     2/ 7      0/2
FB2        15/16     17/40     19/48     1/ 7      1/2
FB3         6/16     21/40     46/48     6/ 7      0/2
FB4         3/16     21/40     11/48     3/ 7      1/2
           -----    -------   -------    -----
Total      40/64     84/160   118/192   12/28 

* - Resource is exhausted

** Local Control Term Resources **

        LCT0     LCT1     LCT2     LCT3     LCT4     LCT5     LCT6     LCT7
FB1     sr                                                             uct1     
FB2                                         clk                        uct4     
FB3                                                                             
FB4     sr                                                                      

Legend:
ce   - clock enable
clk  - clock
oe   - output enable
sr   - set/reset
uct1 - universal control term clock
uct2 - universal control term output enable
uct3 - universal control term preset
uct4 - universal control term reset
LCT0 - oe and/or sr can be mapped to this local control term
LCT1 - oe and/or sr can be mapped to this local control term
LCT2 - oe and/or sr can be mapped to this local control term
LCT3 - sr can be mapped to this local control term
LCT4 - ce and/or clk and/or sr can be mapped to this local control term
LCT5 - clk and/or sr can be mapped to this local control term
LCT6 - clk and/or oe can be mapped to this local control term
LCT7 - clk can be mapped to this local control term

** Global Control Resources **

GCK         UCLK        UOE         UPST        URST        
Used/Tot    Used/Tot    Used/Tot    Used/Tot    Used/Tot
1/4         1/1         0/1         0/1         1/1

GCK  - Global Clock
UCLK - Universal Control Term Clock
UOE  - Universal Control Term Output Enable
UPST - Universal Control Term Preset
URST - Universal Control Term Reset

Signal 'clkin' mapped onto global clock net GCK0.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used     Total 
------------------------------------|-------------------------------------
Input         :    3           3    |  I/O              :    14       28
Output        :   12          12    |  GCK/I            :     2        4
Bidirectional :    0           0    |  
GCK           :    1           1    |  
                 ----        ----
        Total    16           16 

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to map all desired signals into function block, FB3.
   Buffering output signal segment<1> to allow all signals assigned to this
   function block to be placed.
WARNING:Cpld - Unable to map all desired signals into function block, FB3.
   Buffering output signal segment<0> to allow all signals assigned to this
   function block to be placed.
WARNING:Cpld - Unable to map all desired signals into function block, FB3.
   Buffering output signal segment<2> to allow all signals assigned to this
   function block to be placed.
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                   Total Total Loc     Pin   Pin       Pin     Slew Reg Init
Name                     Pts   Inps          No.   Type      Use     Rate State
start_s                  4     6     FB1_1   41    I/O       O       FAST RESET
reset_s                  1     2     FB1_2   40    I/O       O       FAST 
segment<7>               0     0     FB2_3   6     I/O       O       FAST 
segment<0>               1     1     FB3_4   29    I/O       O       FAST 
segment<1>               1     1     FB3_9   28    I/O       O       FAST 
segment<2>               1     1     FB3_10  27    I/O       O       FAST 
segment<3>               19    18    FB3_11  26    I/O       O       FAST 
segment<4>               12    18    FB3_12  25    I/O       O       FAST 
segment<5>               12    18    FB3_13  24    I/O       O       FAST 
catode2                  3     4     FB4_9   18    I/O       O       FAST SET
catode1                  1     3     FB4_10  19    I/O       O       FAST RESET
segment<6>               8     18    FB4_12  21    I/O       O       FAST 

** 28 Buried Nodes **

Signal                   Total Total Loc     Reg Init
Name                     Pts   Inps          State
segment<1>_BUFR          8     18    FB1_3   
segment<2>_BUFR          4     18    FB1_4   
carry<0>                 4     7     FB1_5   RESET
q<1>                     4     6     FB1_6   RESET
q<3>                     4     6     FB1_7   RESET
q<11>                    4     7     FB1_8   RESET
s_a0/stop_out            4     6     FB1_9   RESET
carry<1>                 4     7     FB1_10  RESET
q<5>                     4     6     FB1_11  RESET
q<2>                     3     4     FB1_12  RESET
s_a0/current_state_FFd3  3     3     FB1_13  RESET
q<7>                     4     6     FB1_14  RESET
segment<0>_BUFR          8     18    FB1_15  
q<0>                     3     2     FB1_16  RESET
tlac                     1     1     FB2_2   RESET
q<10>                    3     5     FB2_4   RESET
q<9>                     4     7     FB2_5   RESET
carry<2>                 5     8     FB2_6   RESET
q<13>                    5     8     FB2_7   RESET
q<14>                    4     8     FB2_8   RESET
q<4>                     3     2     FB2_9   RESET
qdiv<2>                  1     2     FB2_10  RESET
qdiv<1>                  1     1     FB2_11  RESET
q<15>                    3     7     FB2_12  RESET
q<12>                    3     4     FB2_13  RESET
qdiv<0>                  0     0     FB2_14  RESET
q<6>                     3     4     FB2_15  RESET
q<8>                     3     3     FB2_16  RESET

** 4 Inputs **

Signal                   Loc     Pin   Pin       Pin     
Name                             No.   Type      Use     
btnsel                   FB2_1   4     I/O       I                
ares                     FB2_2   5     I/O       I                
clkin                            2     GCK/I     GCK              
btn                              1     GCK/I     I                

Legend:
Pin No. - ~ - User Assigned
PU          - Pull Up
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               25/15
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   42/6
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
start_s                       4     FB1_1   41   I/O     O     
reset_s                       1     FB1_2   40   I/O     O     
segment<1>_BUFR               8     FB1_3        (b)     (b)   
segment<2>_BUFR               4     FB1_4        (b)     (b)   
carry<0>                      4     FB1_5        (b)     (b)   
q<1>                          4     FB1_6        (b)     (b)   
q<3>                          4     FB1_7        (b)     (b)   
q<11>                         4     FB1_8   39   I/O     (b)   
s_a0/stop_out                 4     FB1_9   38   TDO/I/O (b)   
carry<1>                      4     FB1_10  37   I/O     (b)   
q<5>                          4     FB1_11  36   I/O     (b)   
q<2>                          3     FB1_12       (b)     (b)   
s_a0/current_state_FFd3       3     FB1_13       (b)     (b)   
q<7>                          4     FB1_14  34   I/O     (b)   
segment<0>_BUFR               8     FB1_15  33   I/O     (b)   
q<0>                          3     FB1_16       (b)     (b)   

Signals Used by Logic in Function Block
  1: ares              10: q<13>             18: q<6> 
  2: btn               11: q<14>             19: q<7> 
  3: carry<0>          12: q<15>             20: q<8> 
  4: carry<1>          13: q<1>              21: q<9> 
  5: catode1           14: q<2>              22: s_a0/current_state_FFd3 
  6: q<0>              15: q<3>              23: s_a0/stop_out 
  7: q<10>             16: q<4>              24: start_s 
  8: q<11>             17: q<5>              25: tlac 
  9: q<12>            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
start_s           XX..X................XXX................ 6       
reset_s           ......................XX................ 2       
segment<1>_BUFR   ....XXXXXXXXXXXXXXXXX...X............... 18      
segment<2>_BUFR   ....XXXXXXXXXXXXXXXXX...X............... 18      
carry<0>          ..X.XX......XXX........X................ 7       
q<1>              ....XX......XXX........X................ 6       
q<3>              ....XX......XXX........X................ 6       
q<11>             ..XXX.XX...........XX................... 7       
s_a0/stop_out     XX..X................XXX................ 6       
carry<1>          ..XXX..........XXXX..................... 7       
q<5>              ..X.X..........XXXX..................... 6       
q<2>              ....XX......X..........X................ 4       
s_a0/current_state_FFd3 
                  XX..X................................... 3       
q<7>              ..X.X..........XXXX..................... 6       
segment<0>_BUFR   ....XXXXXXXXXXXXXXXXX...X............... 18      
q<0>              ....X..................X................ 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               17/23
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   19/29
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB2_1   4    I/O     I     
tlac                          1     FB2_2   5    I/O     I     
segment<7>                    0     FB2_3   6    I/O     O     
q<10>                         3     FB2_4        (b)     (b)   
q<9>                          4     FB2_5        (b)     (b)   
carry<2>                      5     FB2_6        (b)     (b)   
q<13>                         5     FB2_7        (b)     (b)   
q<14>                         4     FB2_8        (b)     (b)   
q<4>                          3     FB2_9   7    TDI/I/O (b)   
qdiv<2>                       1     FB2_10  8    I/O     (b)   clkin
qdiv<1>                       1     FB2_11  9    I/O     (b)   clkin
q<15>                         3     FB2_12       (b)     (b)   
q<12>                         3     FB2_13       (b)     (b)   
qdiv<0>                       0     FB2_14  11   I/O     (b)   clkin
q<6>                          3     FB2_15  12   I/O     (b)   
q<8>                          3     FB2_16       (b)     (b)   

Signals Used by Logic in Function Block
  1: btnsel             7: q<12>             13: q<8> 
  2: carry<0>           8: q<13>             14: q<9> 
  3: carry<1>           9: q<14>             15: qdiv<0> 
  4: carry<2>          10: q<15>             16: qdiv<1> 
  5: q<10>             11: q<4>              17: reset_s 
  6: q<11>             12: q<5>             

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
tlac              X....................................... 1       
segment<7>        ........................................ 0       
q<10>             .XX.........XX..X....................... 5       
q<9>              .XX.XX......XX..X....................... 7       
carry<2>          .XXXXX......XX..X....................... 8       
q<13>             .XXX..XXXX......X....................... 8       
q<14>             .XXX..XXXX......X....................... 8       
q<4>              .X..............X....................... 2       
qdiv<2>           ..............XX........................ 2       
qdiv<1>           ..............X......................... 1       
q<15>             .XXX..XXX.......X....................... 7       
q<12>             .XXX............X....................... 4       
qdiv<0>           ........................................ 0       
q<6>              .X........XX....X....................... 4       
q<8>              .XX.............X....................... 3       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               21/19
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   46/2
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB3_1   32   TCK/I/O       
(unused)                      0     FB3_2   31   I/O           
(unused)                      0     FB3_3        (b)           
segment<0>                    1     FB3_4   29   I/O     O     
(unused)                      0     FB3_5        (b)           
(unused)                      0     FB3_6        (b)           
(unused)                      0     FB3_7        (b)           
(unused)                      0     FB3_8        (b)           
segment<1>                    1     FB3_9   28   I/O     O     
segment<2>                    1     FB3_10  27   I/O     O     
segment<3>                    19    FB3_11  26   I/O     O     
segment<4>                    12    FB3_12  25   I/O     O     
segment<5>                    12    FB3_13  24   I/O     O     
(unused)                      0     FB3_14       (b)           
(unused)                      0     FB3_15       (b)           
(unused)                      0     FB3_16       (b)           

Signals Used by Logic in Function Block
  1: catode1            8: q<15>             15: q<7> 
  2: q<0>               9: q<1>              16: q<8> 
  3: q<10>             10: q<2>              17: q<9> 
  4: q<11>             11: q<3>              18: segment<0>_BUFR 
  5: q<12>             12: q<4>              19: segment<1>_BUFR 
  6: q<13>             13: q<5>              20: segment<2>_BUFR 
  7: q<14>             14: q<6>              21: tlac 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
segment<0>        .................X...................... 1       
segment<1>        ..................X..................... 1       
segment<2>        ...................X.................... 1       
segment<3>        XXXXXXXXXXXXXXXXX...X................... 18      
segment<4>        XXXXXXXXXXXXXXXXX...X................... 18      
segment<5>        XXXXXXXXXXXXXXXXX...X................... 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               21/19
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   11/37
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB4_1   13   TMS/I/O       
(unused)                      0     FB4_2   14   I/O           
(unused)                      0     FB4_3        (b)           
(unused)                      0     FB4_4   16   I/O           
(unused)                      0     FB4_5   17   I/O           
(unused)                      0     FB4_6        (b)           
(unused)                      0     FB4_7        (b)           
(unused)                      0     FB4_8        (b)           
catode2                       3     FB4_9   18   I/O     O     clkin
catode1                       1     FB4_10  19   I/O     O     clkin
(unused)                      0     FB4_11  20   I/O           
segment<6>                    8     FB4_12  21   I/O     O     
(unused)                      0     FB4_13       (b)           
(unused)                      0     FB4_14       (b)           
(unused)                      0     FB4_15       (b)           
(unused)                      0     FB4_16       (b)           

Signals Used by Logic in Function Block
  1: catode1            8: q<15>             15: q<7> 
  2: q<0>               9: q<1>              16: q<8> 
  3: q<10>             10: q<2>              17: q<9> 
  4: q<11>             11: q<3>              18: qdiv<0> 
  5: q<12>             12: q<4>              19: qdiv<1> 
  6: q<13>             13: q<5>              20: qdiv<2> 
  7: q<14>             14: q<6>              21: tlac 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
catode2           X................XXX.................... 4       
catode1           .................XXX.................... 3       
segment<6>        XXXXXXXXXXXXXXXXX...X................... 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_carry0: FDCPE port map (carry(0),carry_D(0),catode1,reset_s,'0','1');
carry_D(0) <= ((NOT start_s AND carry(0))
	OR (start_s AND NOT q(0) AND NOT q(1) AND NOT q(2) AND q(3)));

FDCPE_carry1: FDCPE port map (carry(1),carry_D(1),catode1,reset_s,'0','1');
carry_D(1) <= ((NOT carry(0) AND carry(1))
	OR (carry(0) AND NOT q(4) AND NOT q(5) AND NOT q(6) AND q(7)));

FDCPE_carry2: FDCPE port map (carry(2),carry_D(2),catode1,reset_s,'0','1');
carry_D(2) <= ((NOT carry(0) AND carry(2))
	OR (NOT carry(1) AND carry(2))
	OR (NOT q(8) AND carry(0) AND carry(1) AND NOT q(10) AND NOT q(9) AND 
	q(11)));

FTCPE_catode1: FTCPE port map (catode1,catode1_T,clkin,'0','0','1');
catode1_T <= (qdiv(0) AND qdiv(1) AND qdiv(2));

FDCPE_catode2: FDCPE port map (catode2,catode2_D,clkin,'0',NOT ,'1');
catode2_D <= NOT (catode1
	XOR (qdiv(0) AND qdiv(1) AND qdiv(2)));

FTCPE_q0: FTCPE port map (q(0),start_s,catode1,reset_s,'0','1');

FTCPE_q1: FTCPE port map (q(1),q_T(1),catode1,reset_s,'0','1');
q_T(1) <= (start_s AND q(0))
	XOR (start_s AND q(0) AND NOT q(1) AND NOT q(2) AND q(3));

FTCPE_q2: FTCPE port map (q(2),q_T(2),catode1,reset_s,'0','1');
q_T(2) <= (start_s AND q(0) AND q(1));

FTCPE_q3: FTCPE port map (q(3),q_T(3),catode1,reset_s,'0','1');
q_T(3) <= ((start_s AND q(0) AND q(1) AND q(2))
	OR (start_s AND q(0) AND NOT q(1) AND NOT q(2) AND q(3)));

FTCPE_q4: FTCPE port map (q(4),carry(0),catode1,reset_s,'0','1');

FTCPE_q5: FTCPE port map (q(5),q_T(5),catode1,reset_s,'0','1');
q_T(5) <= (carry(0) AND q(4))
	XOR (carry(0) AND q(4) AND NOT q(5) AND NOT q(6) AND q(7));

FTCPE_q6: FTCPE port map (q(6),q_T(6),catode1,reset_s,'0','1');
q_T(6) <= (carry(0) AND q(4) AND q(5));

FTCPE_q7: FTCPE port map (q(7),q_T(7),catode1,reset_s,'0','1');
q_T(7) <= ((carry(0) AND q(4) AND q(5) AND q(6))
	OR (carry(0) AND q(4) AND NOT q(5) AND NOT q(6) AND q(7)));

FTCPE_q8: FTCPE port map (q(8),q_T(8),catode1,reset_s,'0','1');
q_T(8) <= (carry(0) AND carry(1));

FTCPE_q9: FTCPE port map (q(9),q_T(9),catode1,reset_s,'0','1');
q_T(9) <= (q(8) AND carry(0) AND carry(1))
	XOR (q(8) AND carry(0) AND carry(1) AND NOT q(10) AND NOT q(9) AND 
	q(11));

FTCPE_q10: FTCPE port map (q(10),q_T(10),catode1,reset_s,'0','1');
q_T(10) <= (q(8) AND carry(0) AND carry(1) AND q(9));

FTCPE_q11: FTCPE port map (q(11),q_T(11),catode1,reset_s,'0','1');
q_T(11) <= ((q(8) AND carry(0) AND carry(1) AND q(10) AND q(9))
	OR (q(8) AND carry(0) AND carry(1) AND NOT q(10) AND NOT q(9) AND 
	q(11)));

FTCPE_q12: FTCPE port map (q(12),q_T(12),catode1,reset_s,'0','1');
q_T(12) <= (carry(0) AND carry(1) AND carry(2));

FTCPE_q13: FTCPE port map (q(13),q_T(13),catode1,reset_s,'0','1');
q_T(13) <= ((carry(0) AND carry(1) AND q(12) AND carry(2) AND q(13))
	OR (carry(0) AND carry(1) AND q(12) AND carry(2) AND NOT q(14))
	OR (carry(0) AND carry(1) AND q(12) AND carry(2) AND q(15)));

FTCPE_q14: FTCPE port map (q(14),q_T(14),catode1,reset_s,'0','1');
q_T(14) <= ((carry(0) AND carry(1) AND q(12) AND carry(2) AND q(13))
	OR (carry(0) AND carry(1) AND q(12) AND carry(2) AND q(14) AND 
	NOT q(15)));

FTCPE_q15: FTCPE port map (q(15),q_T(15),catode1,reset_s,'0','1');
q_T(15) <= (carry(0) AND carry(1) AND q(12) AND carry(2) AND q(13) AND 
	q(14));

FTCPE_qdiv0: FTCPE port map (qdiv(0),'1',clkin,'0','0','1');

FTCPE_qdiv1: FTCPE port map (qdiv(1),qdiv(0),clkin,'0','0','1');

FTCPE_qdiv2: FTCPE port map (qdiv(2),qdiv_T(2),clkin,'0','0','1');
qdiv_T(2) <= (qdiv(0) AND qdiv(1));


reset_s <= (NOT start_s AND NOT s_a0/stop_out);

FDCPE_s_a0/current_state_FFd3: FDCPE port map (s_a0/current_state_FFd3,btn,catode1,ares,'0','1');

FTCPE_s_a0/stop_out: FTCPE port map (s_a0/stop_out,s_a0/stop_out_T,catode1,ares,'0','1');
s_a0/stop_out_T <= ((start_s AND btn AND NOT s_a0/current_state_FFd3 AND 
	NOT s_a0/stop_out)
	OR (NOT start_s AND btn AND NOT s_a0/current_state_FFd3 AND 
	s_a0/stop_out));


segment(0)_BUFR <= NOT (((catode1 AND q(8) AND NOT q(10) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND NOT q(8) AND q(10) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND NOT q(1) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND NOT q(0) AND NOT q(1) AND q(2) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND NOT q(5) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND NOT q(4) AND NOT q(5) AND q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(13) AND NOT q(14) AND 
	NOT q(15))
	OR (NOT catode1 AND tlac AND NOT q(12) AND NOT q(13) AND q(14) AND 
	NOT q(15))));


segment(0) <= segment(0)_BUFR;


segment(1)_BUFR <= NOT (((catode1 AND q(8) AND q(10) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND NOT q(8) AND q(10) AND q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND NOT q(1) AND q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND NOT q(0) AND q(1) AND q(2) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND NOT q(5) AND q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND NOT q(4) AND q(5) AND q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(13) AND q(14) AND 
	NOT q(15))
	OR (NOT catode1 AND tlac AND NOT q(12) AND q(13) AND q(14) AND 
	NOT q(15))));


segment(1) <= segment(1)_BUFR;


segment(2)_BUFR <= NOT (((catode1 AND NOT q(8) AND NOT q(10) AND q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND NOT q(0) AND q(1) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND NOT q(4) AND q(5) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND NOT q(12) AND q(13) AND NOT q(14) AND 
	NOT q(15))));


segment(2) <= segment(2)_BUFR;


segment(3) <= NOT ((catode1 AND q(10) AND tlac)
	XOR ((catode1 AND q(1) AND q(3) AND NOT tlac)
	OR (catode1 AND q(2) AND q(3) AND NOT tlac)
	OR (NOT catode1 AND q(5) AND q(7) AND NOT tlac)
	OR (NOT catode1 AND q(6) AND q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(13) AND q(15))
	OR (NOT catode1 AND tlac AND q(14) AND q(15))
	OR (catode1 AND q(8) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND q(1) AND q(2) AND NOT tlac)
	OR (catode1 AND NOT q(0) AND NOT q(1) AND q(2) AND NOT tlac)
	OR (catode1 AND NOT q(10) AND q(9) AND q(11) AND tlac)
	OR (NOT catode1 AND q(4) AND q(5) AND q(6) AND NOT tlac)
	OR (NOT catode1 AND NOT q(4) AND NOT q(5) AND q(6) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND q(13) AND q(14))
	OR (NOT catode1 AND tlac AND NOT q(12) AND NOT q(13) AND q(14))
	OR (catode1 AND NOT q(8) AND q(10) AND q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND NOT q(1) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND NOT q(5) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(13) AND NOT q(14) AND 
	NOT q(15))));


segment(4) <= NOT (((catode1 AND q(8) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(15))
	OR (catode1 AND q(8) AND NOT q(10) AND NOT q(9) AND tlac)
	OR (catode1 AND q(0) AND NOT q(1) AND NOT q(2) AND NOT tlac)
	OR (catode1 AND NOT q(1) AND q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND q(10) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (NOT catode1 AND q(4) AND NOT q(5) AND NOT q(6) AND NOT tlac)
	OR (NOT catode1 AND NOT q(5) AND q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(13) AND NOT q(14))
	OR (NOT catode1 AND tlac AND NOT q(13) AND q(14) AND NOT q(15))));


segment(5) <= NOT (((catode1 AND q(8) AND NOT q(10) AND NOT q(11) AND tlac)
	OR (catode1 AND q(8) AND q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND q(1) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND q(0) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND q(1) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND NOT q(10) AND q(9) AND NOT q(11) AND tlac)
	OR (NOT catode1 AND q(4) AND q(5) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND q(5) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND q(13) AND NOT q(15))
	OR (NOT catode1 AND tlac AND q(12) AND NOT q(14) AND NOT q(15))
	OR (NOT catode1 AND tlac AND q(13) AND NOT q(14) AND NOT q(15))));


segment(6) <= NOT (((catode1 AND NOT q(1) AND NOT q(2) AND NOT q(3) AND NOT tlac)
	OR (catode1 AND NOT q(10) AND NOT q(9) AND NOT q(11) AND tlac)
	OR (NOT catode1 AND NOT q(5) AND NOT q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND NOT q(13) AND NOT q(14) AND NOT q(15))
	OR (catode1 AND q(8) AND q(10) AND q(9) AND NOT q(11) AND tlac)
	OR (catode1 AND q(0) AND q(1) AND q(2) AND NOT q(3) AND NOT tlac)
	OR (NOT catode1 AND q(4) AND q(5) AND q(6) AND NOT q(7) AND NOT tlac)
	OR (NOT catode1 AND tlac AND q(12) AND q(13) AND q(14) AND 
	NOT q(15))));


segment(7) <= '0';

FTCPE_start_s: FTCPE port map (start_s,start_s_T,catode1,ares,'0','1');
start_s_T <= ((start_s AND btn AND NOT s_a0/current_state_FFd3)
	OR (btn AND NOT s_a0/current_state_FFd3 AND NOT s_a0/stop_out));

FTCPE_tlac: FTCPE port map (tlac,'1',btnsel,'0','0','1');


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XCR3064XL-6-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XCR3064XL-6-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 btn                              23 VCC                           
  2 clkin                            24 segment<5>                    
  3 VCC                              25 segment<4>                    
  4 btnsel                           26 segment<3>                    
  5 ares                             27 segment<2>                    
  6 segment<7>                       28 segment<1>                    
  7 TDI                              29 segment<0>                    
  8 WPU                              30 GND                           
  9 WPU                              31 WPU                           
 10 PE                               32 TCK                           
 11 WPU                              33 WPU                           
 12 WPU                              34 WPU                           
 13 TMS                              35 VCC                           
 14 WPU                              36 WPU                           
 15 VCC                              37 WPU                           
 16 WPU                              38 TDO                           
 17 WPU                              39 WPU                           
 18 catode2                          40 reset_s                       
 19 catode1                          41 start_s                       
 20 WPU                              42 GND                           
 21 segment<6>                       43 TIE                           
 22 GND                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xcr3064xl-6-PC44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28